Engineering

Experience

  1. FPGA design engineer

    intoPIX

    Since March 2023 · Belgium

    RTL design and verification for realtime JPEG XS compression pipelines. Altera/Intel and Xilinx toolchains.

    • RTL
    • FPGA
    • Verification
    • Signal processing
    • Real-time

  2. MSc, Electrical Engineering

    UCLouvain

    2017 – 2022 · Louvain-la-Neuve, Belgium

    FPGA engineering, embedded systems, signal processing. A master's thesis aiming to accelerate Transformers Neural Networks inference speed on FPGA.

    • Embedded
    • Signal processing
    • Electronics

Personal projects

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